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M28LV16
16K (2K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
FAST ACCESS TIME: 200ns SINGLE LOW VOLTAGE OPERATION LOW POWER CONSUMPTION FAST WRITE CYCLE: - 64 Bytes Page Write Operation - Byte or Page Write Cycle: 3ms Max ENHANCED END OF WRITE DETECTION: - Data Polling - Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY: - Endurance >100,000 Erase/Write Cycles - Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT SOFTWARE DATA PROTECTION M28LV16 is replaced by the products described on the document M28C16A DESCRIPTION The M28LV16 is a 2K x 8 low power Parallel EEPROM fabricatedwith SGS-THOMSON proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 2.7V to 3.6V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshaking with Data Polling and Toggle Bit. The M28LV16 supports 64 byte page write operation. A Software Data Protection (SDP) is also possible using the standard JEDEC algorithm. Table 1. Signal Names
A0 - A10 DQ0 - DQ7 W E G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground
24
1
PDIP24 (P)
PLCC32 (K)
24
1
SO24 (MS) 300 mils
TSOP28 (N) 8 x 13.4mm
Figure 1. Logic Diagram
VCC
11 A0-A10
8 DQ0-DQ7
W E G
M28LV16 RB *
VSS
AI01567B
Note: * RB function is offered only with TSOP28 package.
November 1997
This is information on a product still in production bu t not recommended for new de sign.
1/17
M28LV16
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI01568
DQ1 DQ2 VSS DU DQ3 DQ4 DQ5
AI01569B
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 24 2 23 3 22 4 21 5 20 6 19 M28LV16 7 18 8 17 9 16 10 15 11 14 12 13
VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A6 A5 A4 A3 A2 A1 A0 NC DQ0
A7 NC NC DU VCC W NC 1 32 A8 A9 NC NC G A10 E DQ7 DQ6 9 M28LV16 25 17
Warning: NC = Not Connected, DU = Don't Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 M28LV16 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 16 15
VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G NC A9 A8 NC W VCC RB NC A7 A6 A5 A4 A3
22
21
28 1
M28LV16
15 14
AI01570
7
8
AI01124C
A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
Warning: NC = Not Connected.
2/17
M28LV16
Table 2. Absolute Maximum Ratings
Symbol TA TSTG VCC VIO VI VESD
(1)
Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
(2)
Value - 40 to 85 - 65 to 150 - 0.3 to 6.5 - 0.3 to VCC +0.6 - 0.3 to 6.5 4000
Unit C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through 1500; MIL-STD-883C, 3015.7
Table 3. Operating Modes
Mode Standby Output Disable Write Disable Read Write
(1)
E 1 X X 0 0
G X 1 X 0 1
W X X 1 1 0
DQ0 - DQ7 Hi-Z Hi-Z Hi-Z Data Out Data In
Note: 1. 0 = VIL; 1 = VIH; X = VIL or VIH.
PIN DESCRIPTION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28LV16 through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28LV16. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. It is offered only with the TSOP28 package. The reader should refer to the M28LV17 datasheet for more information about the Ready/Busy function.
OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28LV16 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either G or E is high. Write Write operations are initiated when both W and E are low and G is high.The M28LV16 supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion.
3/17
M28LV16
Figure 3. Block Diagram
E G W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A10 (Page Address)
ADDRESS LATCH
64K ARRAY
A0-A5
ADDRESS LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING
AI01520
DQ0-DQ7
Page Write Page write allows up to 64 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A6-A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data with a minimum data transfer rate of 1/tWHWH (see Figure 13). If a transition of E or W is not detected within tWHWH, the internal programming cycle will start. Microcontroller Control Interface The M28LV16 provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only. Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. Toggle bit (DQ6). The M28LV16 offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 will toggle from "0" to "1" and "1" to "0" (the first read value is "0") on subsequent attempts to read the memory. When the internal cycle is completed the toggling will stop and the device will be accessible for a new Read or Write operation. Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High indicates time-out after which the write cycle will start and no new data may be input.
DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status
4/17
M28LV16
Figure 5. Software Data Protection Enable Algorithm and Memory Write
WRITE AAh in Address 555h Page Write Instruction (Note 1) Page Write Instruction (Note 1)
WRITE AAh in Address 555h
WRITE 55h in Address 2AAh
WRITE 55h in Address 2AAh
WRITE A0h in Address 555h
WRITE A0h in Address 555h WRITE is enabled
SDP is set
Write Page (1 up to 64 bytes)
SDP ENABLE ALGORITHM
WRITE IN MEMORY WHEN SDP IS SET
AI01509B
Note: 1. MSB Address bits (A6 to A10) differ during these specific Page Write operations.
Figure 6. Software Data Protection Disable Algorithm
WRITE AAh in Address 555h
WRITE 55h in Address 2AAh
Page Write Instruction
WRITE 80h in Address 555h
WRITE AAh in Address 555h
WRITE 55h in Address 2AAh
WRITE 20h in Address 555h
Unprotected State
AI01510
Software Data Protection The M28LV16 offers a software controlled write protection facility that allows the user to inhibit all write modes to the device including the Chip Erase instruction. This can be useful in protecting the memory from inadvertent write cycles that may occur due to uncontrolled bus conditions. The M28LV16is shipped as standard in the "unprotected" state meaning that the memory contents can be changed as required by the user. After the Software Data Protection enable algorithm is issued, the device enters the "Protect Mode" of operation where no further write commands have any effect on the memory contents. The device remains in this mode until a valid Software Data Protection (SDP) disable sequence is received whereby the device reverts to its "unprotected" state. The Software Data Protection is fully nonvolatile and is not changed by power on/off sequences. To enable the Software Data Protection (SDP) the device requires the user to write (with a Page Write) three specific data bytes to three specific memory locations as per Figure 5. Similarly to disable the Software Data Protection the user has to write specific data bytes into six different locations as per Figure 6 (with a Page Write). This complex series ensures that the user will never enable or disable the Software Data Protection accidentally.
5/17
M28LV16
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0V to VCC -0.3V 1.5V
DEVICE UNDER TEST 1.3k VCC -0.3V 0.5 VCC 0V
AI01274
Figure 8. AC Testing Equivalent Load Circuit
VCC
1.8k
Note that Output Hi-Z is defined as the point where data is no longer driven.
OUT
Figure 7. AC Testing Input Output Waveforms
CL = 100pF
CL includes JIG capacitance
AI01396
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 2.7V to 3.6V)
Symbol ILI ILO ICC
(1)
Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VIN VCC E = VIL, G = VIL, f = 5 MHz, VCC = 3.3V E = VIL, G = VIL, f = 5 MHz, VCC = 3.6V E > VCC -0.3V
Min
Max 10 10 8 10 50
Unit A A mA mA A V V V V
ICC2
(1)
VIL VIH VOL VOH
- 0.3 2 IOL = 1 mA IOH = 1 mA 0.8 VCC
0.6 VCC +0.5 0.2 VCC
Note: 1. All I/O's open circuit.
Table 7. Power Up Timing (1) (TA = 0 to 70C or -40 to 85C; VCC = 2.7V to 3.6V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation Write Inhibit Threshold Min 1 10 1.5 2.5 Max Unit s ms V
Note: 1. Sampled only, not 100% tested.
6/17
M28LV16
Table 8. Read Mode AC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 2.7V to 3.6V)
M28LV16 Symbol Alt Parameter Test Condition -200 Min tAVQV tELQV tGLQV tEHQZ
(1)
-250 Min Max 250 250 150 0 0 0 60 60 0 0 0
-300 Min Max 300 300 150 60 60
Unit
Max 200 200 100
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0
ns ns ns ns ns ns
55 55
tGHQZ (1) tAXQX
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 9. Read Mode AC Waveforms
A0-A10 tAVQV E tGLQV G tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA OUT Hi-Z
AI01511B
Note: Write Enable (W) = High
7/17
M28LV16
Table 9. Write Mode AC Characteristics (TA = 0 to 70C or -40 to 85C; VCC = 2.7V to 3.6V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tDVWH tDVEH Alt tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Data Valid before Write Enable High Data Valid before Chip Enable High 50 50 E = VIL, G = VIH G = VIH , W = VIL 100 0 0 0 0 0 0 50 100 0.2 100 3 Test Condition E = VIL, G = VIH G = VIH , W = VIL G = VIH E = VIL W = VIL G = VIH Min 0 0 0 0 0 0 100 100 1 1 1000 Max Unit ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns
8/17
M28LV16
Figure 10. Write Mode AC Waveforms - Write Enable Controlled
A0-A10 tAVWL E tELWL G tGHWL W
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWLDV DQ0-DQ7 DATA IN tDVWH
tWHWL
tWHDX
AI01521
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
A0-A10 tAVEL E tGHEL G tWLEL W
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA IN tDVEH tEHDX
tEHWH
AI01522
9/17
M28LV16
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A10
Addr 0
Addr 1
Addr 2
Addr n
E tPLTS G tWHWL W tWLWH DQ0-DQ7 Byte 0 Byte 1 tWHWH Byte 2 tWHWH Byte n tWHRH
DQ5
Byte n
AI01523
Figure 13. Software Protected Write Cycle Waveforms
G
E tWLWH W tAVEL A0-A5 tWHDX A6-A10 555h tDVWH DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63
AI01515
tWHWL
tWHWH
tWLAX Byte Address
2AAh
555h
Page Address
Note: A6 through A10 must specify the same page address during each high to low transition of W (or E) after the software code has been entered. G must be high only when W and E are both low.
10/17
M28LV16
Figure 14. Data Polling Waveform Sequence
A0-A10
Address of the last byte of the Page Write instruction
E
G
W
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01516
Figure 15. Toggle Bit Waveform Sequence
A0-A10
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI01517
Note: 1. First Toggle bit is forced to '0'
11/17
M28LV16
ORDERING INFORMATION SCHEME Example: M28LV16 -200 K 1 T
Speed -200 -250 -300 200ns 250ns 300ns P
(2)
Package PDIP24 PLCC32
(2)
Temperature Range 1 6 0 to 70 C -40 to 85 C T
Option Tape & Reel Packing
K MS
SO24 300mils
N (1) TSOP28 8 x 13.4mm
Notes: 1. The M28LV16 in TSOP28 package has a Ready/Busy output on pin 1. 2. Packages available on request only.
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
12/17
M28LV16
PDIP24 - 24 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D E E1 e1 eA L S N
PDIP24
mm Min 3.94 0.38 3.56 0.38 1.14 0.20 Max 5.08 1.78 4.06 0.56 1.78 0.30 32.26 14.80 12.50 2.54 - 15.20 3.05 1.02 0 24 16.26 13.97 - 17.78 3.82 2.29 15 0.100 Typ
inches Min 0.155 0.015 0.140 0.015 0.045 0.008 Max 0.200 0.070 0.160 0.021 0.070 0.012 1.270 0.583 0.492 - 0.598 0.120 0.040 0 24 0.640 0.550 - 0.700 0.150 0.090 15
A2 A1 B1 D S
N
A L eA C
B
e1
E1
1
E
PDIP
Drawing is not to scale.
13/17
M28LV16
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 B B1 D D1 D2 E E1 E2 e j N Nd Ne CP
PLCC32
mm Min 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 1.27 0.89 - - 32 7 9 0.10 Max 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - - 0.050 0.035 Typ
inches Min 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - - 32 7 9 0.004 Max 0.140 0.095 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - -
D D1 j
1N
A1
B1
Ne
E1 E
D2/E2 B
e
Nd
A CP
PLCC
Drawing is not to scale.
14/17
M28LV16
SO24 - 24 lead Plastic Small Outline, 300 mils body width
Symb Typ A A1 A2 B C D E e H L N CP
SO24
mm Min 2.46 0.13 2.29 0.35 0.23 15.20 7.42 1.27 - 10.16 0.61 0 24 0.10 Max 2.64 0.29 2.39 0.48 0.32 15.60 7.59 - 10.41 1.02 8 0.050 Typ
inches Min 0.097 0.005 0.090 0.014 0.009 0.598 0.292 - 0.400 0.024 0 24 0.004 Max 0.104 0.011 0.094 0.019 0.013 0.614 0.299 - 0.410 0.040 8
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
15/17
M28LV16
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
Symb Typ A A1 A2 B C D D1 E e L N CP
TSOP28
mm Min Max 1.25 0.20 0.95 0.17 0.10 13.20 11.70 7.90 0.55 - 0.50 0 28 0.10 1.15 0.27 0.21 13.60 11.90 8.10 - 0.70 5 0.022 Typ
inches Min Max 0.049 0.008 0.037 0.007 0.004 0.520 0.461 0.311 - 0.020 0 28 0.004 0.045 0.011 0.008 0.535 0.469 0.319 - 0.028 5
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Drawing is not to scale.
A1
L
16/17
M28LV16
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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